1. Field of the Invention
This invention relates to the manufacture of integrated circuit (IC) devices, and more particularly to an improved lightly doped drain (LDD) transistor device as well as a method of fabricating the same by one ion implantation process.
2. Description of the Prior Art
In submicron transistors, hot electron injection into the gate is a serious reliability problem. Many structures and processes have been proposed in the attempt to design a high speed VLSI manufacturable submicron MOS transistor which exhibits resistance to hot electron degradation.
One such device is the lightly doped drain (LDD) transistor. FIGS. 1A to 1C show, in cross sectional views, the process steps of a prior art LDD transistor. As shown in FIG. 1A, a gate electrode including a gate oxide layer 11 and a polysilicon gate layer 12 is formed on a P type silicon substrate 10. An ion implantation process is performed, which introduces N type impurities, such as arsenic ions, into the polysilicon gate layer 12, so as to increase its conductivity. Next, as shown in FIG. 1B, N type impurities, such as phosphorous ions, are implanted into the P type silicon substrate 10 by using the gate electrode as a mask to form lightly doped N.sup.- source/drain areas 13. Referring to FIG. 1C, sidewall spacers 14 are formed on the side walls of the gate electrode. Other N type impurities, such as arsenic ions, are implanted into the P type silicon substrate 10 using the gate electrode and the sidewall spacers 14 as masks to form heavily doped N.sup.+ source/drain areas 15 completing the prior art LDD transistor. The peak electric field of the transistor is decreased by forming lightly doped N.sup.- source/drain areas 13, thereby increasing the transistor's resistance to hot electron degradation.
However, this technique has some drawbacks. First, as be described above, three ion implantation steps are performed in fabricating a prior art LDD transistor, i.e. (i) to increase the conductivity of the polysilicon gate layer 12, (ii) to form lightly doped N.sup.- source/drain areas 13, and (iii) to form heavily doped N.sup.+ source/drain areas 15. The implantation steps increase the complexity and cycle time for manufacturing the device. Second, the N.sup.+ source/drain areas 15 have a deeper junction depth than do the N.sup.-- source/drain areas 13. As the sizes of devices is reduced with increases in packing densities, the reliability of the transistor is worsen due to punch-through effects.
It is therefore an object of the present invention to provide a transistor device structure having substantially the same junction depth in both heavily doped source/drain areas and in lightly doped source/drain areas to prevent punchthrough effects.
It is another object of the present invention is to provide a method of fabricating an LDD transistor device, which can form both heavily doped source/drain areas and lightly doped source/drain areas and also improve the conductivity of the gate layer in one ion implantation step.